Description
1 DESIGN SPECIFICATION
- There will be a multiplexed Address and Data bus with 8-bits width.
- Both Data and address will be of 8-bits.
- You have to use/implement 8-bit ALU, hence the name 8-bit MIPS.
- You must have to design the following temporary registers:
$zero, $t0, $t1, $t2, $t3, $t4
All these registers will be of 8-bits and the assembly code that will be provided to simulate your design will use only these mentioned registers.
- The Control unit should be microprogrammed. The control signals associated with theoperations should be stored in a special memory (you can use a separate ROM for this purpose) units as Control Words.
- During the simulation, as Assembly Code will be given and you have to convert it intoyour designed MIPS machine code. The conversion process should be automatic. For example, you can write code in your preferred programming language for this conversion.
- Marks will vary according to the efficiency of design.
2 INSTRUCTION SET DESCRIPTION
Instruction ID Instruction Type Instruction
| A | Arithmetic | add |
| B | Arithmetic | addi |
| C | Arithmetic | sub |
| D | Arithmetic | subi |
| E | Logic | and |
| F | Logic | andi |
| G | Logic | or |
| H | Logic | ori |
| I | Logic | sll |
| J | Logic | srl |
| K | Logic | nor |
| L | Memory | sw |
| M | Memory | lw |
| N | Control | beq |
| O | Control | bneq |
| P | Control | j |
3 MIPS INSTRUCTION FORMAT
Our MIPS Instructions will be 20-bits long with the following three formats.
| Opcode | Src Reg 1 | Src Reg 2 | Dst Reg | Shft Amnt |
| 4-bits | 4-bits | 4-bits | 4-bits 4-bits | |
| Opcode | Src Reg 1 | Src Reg 2 | Address / Immediate | |
| 4-bits | 4-bits | 4-bits | 8-bits | |
| Opcode | Target Jump Address | 0 | 0 | |
- R-type
- I-type
- J-type
4-bits 8-bits 4-bits 4-bits
4 MEMORY CONSIDERATIONS
You need to consider three types of memory:
- Instruction Memory (accessed through program counter, pc)
- Data Memory (accessed through address)
- Stack Memory (accessed through stack pointer, sp Sample instruction: sw $t0, 0($sp) or lw $t1, 4($sp))
5 INSTRUCTION SET ASSIGNMENT
The opcodes of the instruction will be between 0 to 15 based on the sequence of instruction id given below. Sequence ABCDEFGHIJKLMNOP means add instruction’s opcode will be 0, addi instruction’s opcode will be 1, sub instruction’s opcode will be 2, and so on.
| 1 | LEJBHKFIGACONMPD | AGOJPKFNCIMBLEHD | GDOMBACPKFLENHJI | AEHKFCIJLODNPBMG |
| 2 | MPNGOKCJILFDBEAH | JFMGKLNEPBCHDAIO | DCJOGPAFBINHEKLM | MPOEGBJAKHCILNFD |
| 3 | OFLAJDBCEKIMNHPG | HCNJKAGMBDEFPIOL | EFLAIDPKCHOBNGMJ | MDHKCPOALIENBGFJ |
| 4 | FELDBNJKAIOHMGPC | NFPKOLAJEIBHGMCD | PGMAJLBFHNCKOEDI | PJDKHOBAGNCFLIME |
| 5 | HGIADLKMJBFECOPN | CKPIBEJHDLFMGANO | PEJHODFLNAKGBIMC | MBJNKEFOGDHCALPI |
| 6 | IDFGJMLHOKNCBEAP | GOCFJDBLEMIAHPNK | PNDBCAMLHIJOKEGF | CDEFGMBOAJHIKPLN |
6 REPORT CONTENT
Contents of the report are recommended as follows:
- Introduction
- Instruction Set
- Circuit Diagram printed in drawing paper (Will discuss about this point in the class)
- How to write and execute a program in this machine
- Special Features Implemented if any (may carry bonus marks)
- ICs used with their count
- Discussion
