Description
In this assignment, you will design, simulate (in S/W), and implement (in H/W) a modified and reduced version of the MIPS instruction set.
1 DESIGN SPECIFICATION
- The Address bus will be of 8 bits.
- The Data bus will be of 4 bits.
- You have to implement 4-bit ALU, hence the name 4-bit MIPS.
- You have to design the following temporary registers:
$zero, $t0, $t1, $t2, $t3, $t4
All these registers will be of 4-bits, and the assembly code that will be provided to simulate your design will use only these mentioned registers.
- The Control unit should be microprogrammed. The control signals associated with theoperations should be stored in a special memory (you can use a separate ROM for this purpose) units as Control Words.
- During the simulation, an Assembly Code will be given, and you have to convert it intoyour designed MIPS machine code. The conversion process should be automatic. For this conversion, you can write code in your preferred programming language.
- Marks will vary according to the efficiency of design.
2 INSTRUCTION SET DESCRIPTION
Instruction ID Instruction Type Instruction
| A | Arithmetic | add |
| B | Arithmetic | addi |
| C | Arithmetic | sub |
| D | Arithmetic | subi |
| E | Logic | and |
| F | Logic | andi |
| G | Logic | or |
| H | Logic | ori |
| I | Logic | sll |
| J | Logic | srl |
| K | Logic | nor |
| L | Memory | lw |
| M | Memory | sw |
| N | Control | beq |
| O | Control | bneq |
| P | Control | j |
3 MIPS INSTRUCTION FORMAT
Our MIPS Instructions will be 16-bits long with the following four formats.
| Opcode | Src Reg 1 | Src Reg 2 | Dst Reg |
- R-type
4-bits 4-bits 4-bits 4-bits
| Opcode | Src Reg 1 | Dst Reg | Shamt |
- S-type
| 4-bits | 4-bits | 4-bits | 4-bits |
| Opcode | Src Reg 1 | Src Reg 2/Dst Reg | Addr./Immdt. |
- I-type
| 4-bits | 4-bits 4-bits | 4-bits |
| Opcode | Target Jump Address | 0 |
- J-type
4-bits 8-bits 4-bits
4 MEMORY CONSIDERATIONS
You need to consider three types of memory:
- Instruction Memory (accessed through the program counter, PC)
- Data Memory (accessed through address)
- Bonus: Stack Memory (accessed through stack pointer, sp. Sample instruction: sw $t0, 0($sp) or lw $t1, 4($sp)), this will be used for push and pop
5 INSTRUCTION SET ASSIGNMENT
The opcodes of the instruction will be between 0 to 15 based on the sequence of instruction id given below. Sequence ABCDEFGHIJKLMNOP means add instruction’s opcode will be 0, addi instruction’s opcode will be 1, sub instruction’s opcode will be 2, and so on.
| 1 | GACONMPDLEJBHKFI | CIMBLEHDAGOJPKFN | KFLENHJIGDOMBACP | LODNPBMGAEHKFCIJ |
| 2 | ILFDBEAHMPNGOKCJ | PBCHDAIOJFMGKLNE | BINHEKLMDCJOGPAF | KHCILNFDMPOEGBJA |
| 3 | EKIMNHPGOFLAJDBC | BDEFPIOLHCNJKAGM | CHOBNGMJEFLAIDPK | LIENBGFJMDHKCPOA |
| 4 | AIOHMGPCFELDBNJK | EIBHGMCDNFPKOLAJ | HNCKOEDIPGMAJLBF | GNCFLIMEPJDKHOBA |
| 5 | JBFECOPNHGIADLKM | DLFMGANOCKPIBEJH | NAKGBIMCPEJHODFL | GDHCALPIMBJNKEFO |
| 6 | OKNCBEAPIDFGJMLH | EMIAHPNKGOCFJDBL | HIJOKEGFPNDBCAML | AJHIKPLNCDEFGMBO |
