Description
In this assignment, you have to design an 8-bit processor that implements the MIPS instruction set. Each instruction will take 1 clock cycle to be executed. The length of the clock cycle will be long enough to execute the longest instruction in the MIPS instruction set. The main components of the processor are as follows: instruction memory, data memory, register file, ALU, and a control unit. Additional components such as multiplexors, adders etc can added as required by your design.
1 DESIGN SPECIFICATION
- Address bus and data bus are multiplexed.
- Each of data and address has a size of 8-bits.
- An 8-bit ALU will be required, hence the name 8-bit MIPS.
- The register file must include the following temporary registers:
$zero, $t0, $t1, $t2, $t3, $t4
Each register has a size of 8-bits. The assembly code that will be provided to simulate your design will use only the above mentioned registers.
- The control unit should be micro-programmed. The control signals associated with the operations should be stored in a special memory (you can use a separate ROM for this purpose) units as Control Words.
- All clocks required in the circuit must be provided from a single clock source. Each in-struction should be fetched and executed in a single clock cycle.
- Your design will be evaluated based on accuracy (correct flow of execution for eachimplemented instruction), completeness (all assigned instructions have been implemented), and efficiency (minimizing the number of ICs used, automated assembler).
2 INSTRUCTION SET DESCRIPTION
Instruction ID Category Type Instruction
| A | Arithmetic | R | add |
| B | Arithmetic | I | addi |
| C | Arithmetic | R | sub |
| D | Arithmetic | I | subi |
| E | Logic | R | and |
| F | Logic | I | andi |
| G | Logic | R | or |
| H | Logic | I | ori |
| I | Logic | R | sll |
| J | Logic | R | srl |
| K | Logic | R | nor |
| L | Memory | I | sw |
| M | Memory | I | lw |
| N | Control-conditional | I | beq |
| O | Control-conditional | I | bneq |
| P | Control-unconditional | J | j |
3 MIPS INSTRUCTION FORMAT
Our MIPS Instructions will be 20-bits long with the following three formats.
| Opcode | Src Reg 1 | Src Reg 2 | Dst Reg | Shft Amnt |
- R-type
| 4-bits | 4-bits | 4-bits | 4-bits 4-bits |
| Opcode | Src Reg | Dst Reg | Address / Immediate |
- I-type
| 4-bits | 4-bits 4-bits | 8-bits | ||
| Opcode | Target Jump Address | 0 | 0 | |
- J-type
4-bits 8-bits 4-bits 4-bits
4 MEMORY CONSIDERATIONS
ForasinglecycleimplementationofMIPSinstructionset,youneedtohavetwoseparatememory units for instruction and data.
- Instruction Memory is accessed through an 8-bit address which is stored in an 8-bit Pro-gram Counter (PC) register. Each access to the instruction memory provides 20-bit (instruction) data.
- Data Memory is also accessed through an 8-bit address.
5 INSTRUCTION SET ASSIGNMENT
The opcodes of the instruction will be between 0 to 15 based on the sequence of instruction id given below. Sequence ABCDEFGHIJKLMNOP means add instruction’s opcode will be 0, addi instruction’s opcode will be 1, sub instruction’s opcode will be 2, and so on.
| 1 | FBKOINHDACFGELMP | GHCIAFEBFKDPLNOM | IEMFPDFNKLCHGBAO | PLIADGFBKFNCEMOH |
| 2 | HCAGNMIFDBOFEPKL | GAPOLNDMFKHCFEIB | KAGBLIPFNFMDCHEO | AKEHPDFOBCNLGMFI |
| 3 | HOCIKFEBAFNLDGMP | FDNKLIMFEOPBGCHA | IONHAKEBDLMFPCFG | GBFOLNAIEDFMKHCP |
| 4 | IOECDBPNKMGHFFLA | HFABDNKMPOLIECFG | AHLOGBFNMFDPECKI | HBDMNEKCPLAIGFFO |
| 5 | LNKIFHPBECOGFMAD | KILHFDPNBMFGEACO | EFNPOCDBIGAHMFKL | PAGIFOEHFNMDCLKB |
| 6 | POFMBNDECAGIHKLF | FLHGNIKAFBCMPEDO | MICHBDFLOAGFKPNE | CLIFMHOEBKFGDNAP |
6 EXTRA FEATURES
You have to implement push and pop operations in your MIPS design using a Stack. To achieve this task, the stack memory will be shared with the data memory in the following way. The data memory should start from the minimum address (0x00) and grow to the increasing memory addresses. On the contrary, the stack memory should start from the maximum address (0xFF) and grow to the decreasing memory addresses. The top of your stack will be held by a stack pointer ($sp). Initially $sp will hold an address of 0xFF (highest address of the stack memory). The push and pop operations will be used in the provided assembly code according to the following table and you have to implement them using your MIPS instruction set.
| Instruction | Description |
| push $t0 | mem[$sp] = $t0 |
| push 3($t0) | mem[$sp] = mem[$t0+3] |
| pop $t0 | $t0 = mem[$sp] |
7 SIMULATION
To simulate your design, an assembly code will be used. Before starting the simulation, you have to convert the given assembly code into MIPS machine code and load the machine code into the instruction memory. The conversion process must be automatic. For example, you can write code in your preferred programming language for this conversion.
