[SOLVED] CPE526-Homework 4

Description

Take the VHDL model of the arbiter provided and instantiate it in a SystemVerilog top module that also contains an interface, 4 instances of the provided request model, 4 test programs (one for each request device) and one test program that randomly generates resets for the system. Create random variables for the (1) number of cycles consumed before a device generates a request, (2) the number of cycles a request is kept high, (3) the number of cycles consumed before a reset is generated, and (4) the number of cycles the reset is asserted.

Use the following constraints:

(1) Range: 101 – 299             (2) Range: 1 – 100            (3) Range: 301 – 499    (4) Range: 4 – 9

Even though you are using different instantiations of a class, the method will give the same results. So, force the system to have different values by changing the number of calls to randomize in each test program.

p.randomize();

p.randomize();

p.randomize();

…