[SOLVED] CPE526-Homework 1 Simulating Multiple Architectures

Description

Consider a code converter circuit that converts BCD 84-2-1 to BCD 8421.

B3B2B1B0          E3E2E1E0

0 0 0 0                   0 0 0 0

0 0 0 1                   1 1 1 1

0 0 1 0                   1 1 1 1

0 0 1 1                   1 1 1 1

0 1 0 0                   0 1 0 0

0 1 0 1                   0 0 1 1

0 1 1 0                   0 0 1 0

• 1 1 1             0 0 0 1
• 0 0 0                1 0 0 0

1 0 0 1                   0 1 1 1

1 0 1 0                   0 1 1 0

1 0 1 1                   0 1 0 1

1 1 0 0                   1 1 1 1

1 1 0 1                   1 1 1 1

1 1 1 0                   1 1 1 1

1 1 1 1                   1 0 0 1

B₃B₂B₁B₀ represents the 4-bit BCD 84-2-1 input and E₃E₂E₁E₀ represents the 4-bit BCD 8421 output. For invalid BCD 84-2-1 inputs, all 1s are output as an error indication. You will find a zip file in Canvas that contains the following:

1. A VHDL entity declaration for the converter.
2. An algorithmic behavioral architectural body for the converter.
3. A data flow behavioral architectural body for the converter.
4. A structural architectural body for the converter.
5. A test bench entity that ties the entity to a pulse generator that generates all possible combinations of the inputs.
6. Three configuration files

i.Test bench for the behavioral architecture

ii.Test bench for the dataflow architecture

iii.Test bench for the structural architecture