Description
Consider a parking lot with a single entry and exit gate. Two pairs of sensors (a, b) are used to monitor the activity of cars. When an object is detected by a sensor, its output is asserted to 1. By monitoring the events of two sensors, we can determine whether a car is entering or exiting or whether a pedestrian is passing through. For example, the following sequence indicates that a car enters the lot:
- Initially, both sensors are off (i.e., the a and b signals are 00)
- Sensor a is triggered (i.e., the a and b signals are 10)
- Both sensors are triggered (i.e., the a and b signals are 11)
- Sensor a is off (i.e., the a and b signals are 01)
- Both sensors become off (i.e., the a and b signals are 00) Design a parking lot occupancy counter as follows:
- Design a FSM with two input signals, a and b, and two output signals, car_enter and car_exit. The car_enter and car_exit signals assert one clock cycle when a car enters and one clock cycle when a car exists the lot, respectively
- Include your state diagram or ASM chart with your submission
- Derive the HDL code for the FSM
- Figure out a way to use the car_enter and car_exit signals along with a single up/down counter to show the total number of cars in the parking lot
- Implement the system on the FPGA board. Use two debounced pushbuttons to mimic the operation of the two sensor outputs. Display the content of the counter on the seven-segment display.
