Description
This project will be relatively simple, but we would like you to get a clear idea of what you would like to build for your FSM. If you plan ahead now and make it scalable, it would keep things easier as the semester progresses.
In this project, you would build a Finite State Machine (FSM) using System Verilog.
Project Requirements:
- Code your FSM in Behavioral System Verilog. Be creative in your FSM but at least 10 states are required.
- Choose your FSM for a practical application. Examples include Elevator operation, Vending Machines, Bank ATMs, Traffic controller, Convolutional Encoders, Surveillance drones, etc. Be creative; pick something interesting. By not specifying which FSM to use in this project, we are hoping to see many different implementations in the class. And we know that you are smart enough not to copy your code from web (Your code will be submitted to a plagiarism checker)!
- One test bench and at least one module for your FSM
- Clear comments to your code
Report Layout
- Name, student number and project title on the first page of your project report.
- A paragraph on the general description of your FSM [10].
- A test bench and at least one module for your FSM. You can have more than two modules if your FSM requires it. Define the input and output of each module and a purpose/description of each state for each module. In your test bench, please put comments on how this will test your FSM. [20]
- A block diagram of FSM module(s). Please label all inputs and outputs. [10]
- A block diagram of how the module(s) and test bench are connected. [10]
- A state diagram of your FSM with data flow. [10]
- A copy of your code (in Font Size 8) [10] [as a separate file]
- Simulation waveform results [30]
