[SOLVED] EECS101001 -HW7

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Logic Design

1

  1. The memory units that follow are specified by the number of words times the number of bits per word. (1) How many address lines and input-output lines are needed in each case?

(2) Give the number of bits stored in the memories in each case. (a) 2M x 16 (b) 2G x 8.

 

  1. Design a 8×5 RAM.

 

  1. A 12-bit Hamming code word containing 8 bits of data and 4 parity bits is read from the memory. What is the original 8-bit data word that was written into memory if the 12-bit word read out is as: (a) 011001000110 (b) 101110110100

 

  1. Tabulate the truth table for an 8×4 ROM that implements the Boolean functions.
    • A(X, Y, Z) = Σm(1, 2, 4)
    • B(X, Y, Z) = Σm(3, 5, 7)
    • C(X, Y, Z) = Σm(1, 2, 6, 7)
    • D(X, Y, Z) = Σm(2, 3, 5, 6, 7)

 

  1. FPGA: The logic cell has four inputs (A, B, C, D) and one output (Z).
    • Draw the logic diagram of a simple logic cell with 4-bit inputs and 1-bit outputs.
  • Explain how the logic cell can finish the sum function in a full adder. (Z=A+B+C)