Description
Task 1: S′-R′ Latch (5 points)
An S′-R′ latch operates according to the following function table.
Write a VHDL program to implement an S′-R′ latch using structural design. Please make sure you use the entity declaration provided below. No points would be given if failed to follow it.
Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names, signal values, and the time.
Task 2: S-R Latch with enable (5 points)
An S-R latch with enable operates according to the following function table.
It can be built based on a S′-R′ Latch. Write a VHDL program to implement the SR Latch with Enable using structural design. Please make sure you use the entity declaration provided below. No points would be given if failed to follow it.
Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names, signal values, and the time.
Task 3: D-Latch (5 points)
Build a D latch in Xilinx according to the following function table.
The D latch can be built based on an S-R Latch with Enable. Write a VHDL program to implement the D latch using structural design. Please make sure you use the entity declaration provided below. No points would be given if failed to follow it.
Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names, signal values, and the time.
Task 4: Negative Edge Triggered D Flip-Flop (5 points)
Build a negative edge triggered D flip-flop in Xilinx according to the following function table.
The negative edge triggered D flip-flop can be built based on the D latch in the previous task. Write a VHDL program to implement the negative edge triggered D flip-flop using structural design. Please make sure you use the entity declaration provided below. No points would be given if failed to follow it.
Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names, signal values, and the time.
