[SOLVED] CS39001-Assignment 2 Verilog Design of Binary Adders

Description

1. [Ripple Carry Binary Adder] Design (using Verilog), simulate, and synthesize for any target FPGA supported by your version of Vivado an 8-bit ripple carry adder. Your design should consist of a cascade of eight full adders. Write a testbench to simulate it. After logic synthesis, note its hardware requirement and critical path delay from the synthesis report. The interface of your design should be:

module ripple carry adder (input [7:0] a, input [7:0] b, input cin, output [7:0] sum,

output cout);.

2. [Hybrid Binary Adder] Design (using Verilog), simulate, and synthesize for any target FPGA supported by your version of Vivado, an 8-bit hybrid adder. Your design should consist of a cascade of two 4-bit carry lookahead adders. Write a testbench to simulate it. After logic synthesis, note its hardware requirement and critical path delay from the synthesis report. The interface of your design should be:

module hybrid adder (input [7:0] a, input [7:0] b, input cin, output [7:0] sum, output

cout);.

3. [Bit-serial Binary Adder] Design (using Verilog), simulate and synthesize for any target FPGA supported by your version of Vivado, a bit-serial adder. Write a testbench to simulate it. After logic synthesis, note its hardware requirement and critical path delay from the synthesis report. The input-side shift registers used in the datpath of your bit-serial adder should have “parallel load” capabilities such that the 8-bit operands can be loaded in each of them in one clock cycle. Come up with a proper interface of your design, which includes all input control signals and a clock signal.