Description
Lab 5 – VHDL for Sequential Circuits: Implementing a customized State Machine
1 Objectives
• To simulate and verify the operation of a sequential circuit.
• To learn the difference between Mealy and Moore machines and express the FSMs with different state assignments.
2 Pre-Lab Preparation
3. Design the logic equations for each of the Flip-Flop inputs described in Figure 3.
5. Create a file lab5.vhd.
3 Laboratory Work
1. Create the subdirectory lab5 in your work directory, and copy the file lab5.vhd to the subdirectory.
2. Consider the 9 digits of the student identifier D = {d1, d2, d3, d4, d5, d6, d7, d8, d9} in its general representation. Then, as an example, a student with identifier: 500435429 will follow the sequence as in Table 1.
3. The corresponding Mealy/Moore machine state diagrams for representing student ID in Table 1 is depicted as in Figure 2. Your circuit design must handle non-valid states and non-valid student identifier cases by displaying an “E” in the seven segment display.
4. Modify and compile your design (Figures 4 and 5).
NOTE: Re-use the 7-segment module from Lab3 to display states and student identifier digits.
2 | P a g e
student_id_digit_1 d1 5
student_id_digit_2 d2 0
student_id_digit_3 d3 0
student_id_digit_4 d4 4
student_id_digit_5 d5 3
student_id_digit_6 d6 5
student_id_digit_7 d7 4
student_id_digit_8 d8 2
student_id_digit_9 d9 9
Table 1 Digits Representing Student Identification number
Figure 1 State Diagram Assignments
Figure 2 FSM Types for Representing Student Identification Number
Figure 3 Finite State Machine
Figure 4 VHDL Code Template
An example of the connections in the block diagram is represented in Figure 5
Figure 5 Block Diagram for FSM
