Description
This lab introduces the idea of the pipelining technique for building a fast CPU. The students will obtain experience with the design implementation and testing of the first four stages (Instruction Fetch, Instruction Decode, Instruction Execute, Memory) of the five-stage pipelined CPU using the Xilinx design package for FPGAs.
- Pipelining
As described in lab 4
- Circuits of the Instruction Fetch Stage
As described in lab 4
- Circuits of the Instruction Decode Stage
As described in lab 4
- Circuits of the Execution Stage
As described in lab 5
- Circuits of the Memory Access Stage
As described in lab 5
6. Circuits of the Write Back Stage
Referring to Figure 1, in the fifth cycle the first instruction entered the WB stage. The memory data is selected and will be written into the register file at the end of the cycle. All the control signal have a prefix “w”. The second instruction entered the MEM stage; the third instruction entered the EXE stage; the fourth instruction is being decoded in the ID stage; and the fifth instruction is being fetched in the IF stage. All the six pipeline registers are updated at the end of the cycle (the destination register is considered as the six pipeline register). Then the first instruction is committed. In each of the forth coming clock cycles, an instruction will be commited and a new instruction will enter the pipeline. We use the structure shown in Figure 1 as a baseline for the design of our pipelined CPU.
Pipeline write back (WB) stage
- Table 1 lists the names and usages of the 32 registers in the register file.
Table 1 MIPS general purpose register
| $zero | 0 | Constant 0 |
| $at | 1 | Reserved for assembler |
| $v0, $v1 | 2, 3 | Function return values |
| $a0 – $a3 | 4 – 7 | Function argument values |
| $t0 – $t7 | 8 – 15 | Temporary (caller saved) |
| $s0 – $s7 | 16 – 23 | Temporary (callee saved) |
| $t8, $t9 | 24, 25 | Temporary (caller saved) |
| $k0, $k1 | 26, 27 | Reserved for OS Kernel |
| $gp | 28 | Pointer to Global Area |
| $sp | 29 | Stack Pointer |
| $fp | 30 | Frame Pointer |
| $ra | 31 | Return Address |
- Table 2 lists some MIPS instructions that will be implemented in our CPU
Table 2 MIPS integration instruction
- Initialize the first 10 words of the Data memory with the following HEX values:
A00000AA
10000011
20000022
30000033
40000044
50000055
60000066
70000077
80000088
90000099
- Write a Verilog code that implement the following instructions using the design shown in Figure 1. Write a Verilog test bench to verify your code: (You have to show all the signals written into and out from the MEM/WB register and the inputs to the Regfile block in your simulation outputs)
instruction comment
lw $2, 00($1) # $2 ßß memory[$1+00]; load x[0] lw $3, 04($1) # $3 ßß memory[$1+04]; load x[1] lw $4, 08($1) # $4 ßß memory[$1+08]; load x[2] lw $5, 12($1) # $5 ßß memory[$1+12]; load x[3] add $6, $2, $10
Assume that the register $1 has the value of 0
